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module hw3(clk,seed,enable,D0,D1,D2,D3,D4,D5);
input clk,seed,enable;
output D0,D1,D2,D3,D4,D5;
wire x1;
reg D0,D1,D2,D3,D4,D5,mux_out;
assign x1=D4^D5;
always@(posedge clk)
begin
D0 <= mux_out;
D1 <= D0;
D2 <= D1;
D3 <= D2;
D4 <= D3;
D5 <= D4;
end
always@(posedge clk)
begin
if(enable) mux_out<=x1;
else mux_out<=seed;
end
endmodule